CPU in Logisim
Pipelined version of logic circuit of a 1 clock cycle CPU
This was a project done in partnerrship with Nurzhan Abdrassilov for CS61C - Computer Architecture course. As a part of this project, we have engineered the optimal pipelined version of the CPU cycle circuit, including all the subcircuits, such as ALU, ReFile, Immediate Generator, Branch Comparator, Store, Load and Program Counter.
The circuit was built in Logisim - a tool that allows to connect multiple logic gates (AND, OR, etc.) together to form larger circuits. As a result, we were able to run all the RISC-V ASSEMLY language instructions on our CPU.